1. Field of the Invention
The invention relates to a multifunctional highly integrated, high capacity semiconductor device having unit circuit-block with respective separate functions, and connecting circuits for the conjunction (i.e., interconnection) of the circuit-blocks.
Remarkable advances in the field of semiconductor devices have been accomplished by the development of fine-forming techniques, whereby the area of use of the semiconductor devices has been rapidly enlarged, and a proportion occupied by custom integrated circuits, called application specific integrated circuits (ASICs), has increased more and more.
In the case of ASICs, in addition to the performance thereof, a shortening of the time for delivery of products to a customer is very important. The invention provides a method of achieving a reduction of the time needed for the delivery of ASICs.
2. Description of the Related Art
Prior art ASICs are manufactured by one of the following methods: 1) a gate array method in which bulk elements such as transistors are pre-formed, and an interconnection thereof is then made to satisfy the user's requirements; 2) a standard cell method in which basic circuit elements are previously proposed to a user, a bulk design of a chip is made, based on the user's requirements, and the production thereof is then started; and 3) a full custom method in which the design of a chip is based, from the beginning, on the user's specification.
Each of these methods has advantages and disadvantages. For example, the gate array method provides a short delivery time, but is wasteful of unused elements, as all elements are not used when meeting a user's requirements; the full custom method eliminates this waste of elements, but requires a long delivery time, as it is necessary to design the whole chip, so as to be manufactured as demanded by the customer.
Under the above-mentioned situation, the standard cell method is expected to dominate the ASIC manufacturing art, as it provides a balance of delivery time and wastage of unnecessary elements.
Nevertheless, even in the standard cell method, it is important to further reduce the time needed for delivery of products to a customer, because under present conditions, products are made by following a sequence of processes demanded by a customer, a bulk design of the chip, forming required masks, and production of the chip, so that this method merely reduces the amount of design procedures compared with the full custom method. Moreover, since it is necessary to an form all masks according to individual customer's demands, the cost of forming the masks is added to the chip price, and if the number of chips required is small, the proportion of the cost of a mask per chip is increased, and thus the chip cost becomes higher than that produced by the gate array method.
The electrode connections of a common DRAM (dynamic random access memory) are now composed of four layers of polycrystalline silicon film and two layers of aluminum film, and thus the procedure for bulk manufacture of usual storage elements is very long, e.g., from scores of steps to a hundred and scores of steps. Currently, it is difficult to mount such large capacity storage elements on an ASIC, because of the large number of steps required by this procedure.
In the prior art, a divided exposure of a resist layer formed on a semiconductor chip is used when a single exposure operation cannot cover the whole of the chip area to be exposed to an energy ray, due to limitations in the size of the lens used for the exposure. In this case, the individually exposed areas are fully merged at the common boundary line therebetween, to thus form a single area having an intended function as a whole.
By contrast, the chip of the semiconductor device of the present invention is provided with two or more unit circuit-blocks or cells, each having a separate function, which are not interconnected by an underlying layer in which the unit circuit-blocks are present but which are connected to each other by interconnections in an overlaying layer formed on the underlying layer. To the applicant's knowledge, semiconductor devices having such a construction have not been disclosed in the prior art.